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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
March 2010
FAN103 Primary-Side-Regulation PWM Controller (PWM-PSR)
Features
Low Standby Power Under 30mW High Voltage Startup Fewest External Component Counts Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Green-Mode Function: Linearly-Decreasing PWM Frequency Fixed PWM Frequency at 50kHz with Frequency Hopping to Solve EMI Problem Cable Compensation in CV Mode Peak-Current-Mode Control in CV Mode Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection with Auto Restart VDD Under-Voltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 15V Fixed Over-Temperature Protection with Auto Restart Available in the 8-Lead SOP Package
Description
This third-generation Primary-Side-Regulation (PSR) and highly integrated PWM controller provides several features to enhance the performance of low-power flyback converters. The proprietary topology, TURECURRENTTM, of FAN103 enables precise CC regulation and simplified circuit for battery charger applications. A low-cost, smaller and lighter charger results as compared to a conventional design or a linear transformer. To minimize standby power consumption, the proprietary green-mode function provides off-time modulation to linearly decrease PWM frequency under light-load conditions. This green mode assists the power supply in meeting the power conservation requirement. By using the FAN103, a charger can be implemented with few external components and minimized cost. A typical output CV/CC characteristic envelope is shown in Figure 1.
VO
Maximum Minimum Before Cable Compensation After Cable Compensation
Applications
Battery chargers for cellular phones, cordless phones, PDA, digital cameras, power tools, etc. Replaces linear transformer and RCC SMPS
IO
Figure 1. Typical Output V-I Characteristic
Ordering Information
Part Number
FAN103MY
Operating Temperature Range
-40C to +105C
Eco Status
Green
Package
8-Lead, Small Outline Package (SOP-8)
Packing Method
Tape & Reel
For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
www.fairchildsemi.com
FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Application Diagram
Rsn L1 Rsn2 D1 RF AC Input D2 D3 C1 C2 D4 Rsn1 CVDD DFa CVS R1 R2
MOSFET
Csn2
T1 Csn Dsn DF CO1 CO2 Rd DC Output
3 VDD 7 N.C 8 HV 6 GND
VS 5 GATE 2 CS 1 COMR 4
RGATE
Rcs RSENSE
CCR
Figure 2.
Typical Application
Internal Block Diagram
Figure 3. Functional Block Diagram
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3 www.fairchildsemi.com 2
FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Marking Information
F: Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M=SOP) P: Y=Green Package M: Manufacture Flow Code
Figure 4.
Top Mark
Pin Configuration
Figure 5. Pin Configuration
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Name
CS GATE VDD COMR VS GND NC HV
Description
Current Sense. This pin connects a current sense resistor, to detect the MOSFET current for peak-current-mode control in CV mode, and provides the output-current regulation in CC mode. PWM Signal Output. This pin uses the internal totem-pole output driver to drive the power MOSFET. It is internally clamped below 15V. Power Supply. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external VDD capacitor of typically 10F. The threshold voltages for startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA. Cable Compensation. This pin connects a capacitance between the COMR and GND pins for compensation voltage drop due to output cable loss in CV mode. Voltage Sense. This pin detects the output voltage information and discharge time based on voltage of auxiliary winding. Ground No Connect High Voltage. This pin connects to bulk capacitor for high-voltage startup.
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VHV VVDD VVS VCS VCOMV VCOMI PD JA JC TJ TSTG TL HV Pin Input Voltage DC Supply Voltage
(1)(2)
Parameter
Min.
Max.
500 30
Unit
V V V V V V mW C/W C/W C C C
VS Pin Input Voltage CS Pin Input Voltage Voltage Error Amplifier Output Voltage Current Error Amplifier Output Voltage Power Dissipation (TA<50C) Thermal Resistance (Junction-to-Air) Thermal Resistance (Junction-to-Case) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Electrostatic Discharge Capability Human Body Model (Except HV Pin), JEDEC-JESD22_A114 Charged Device Model (Except HV Pin), JEDEC-ESD22_C101
-0.3 -0.3 -0.3 -0.3
7.0 7.0 7.0 7.0 660 150 39
-40 -55
+150 +150 +260 4.50
ESD
kV 1.25
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Unit
C
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Electrical Characteristics
Unless otherwise specified, VDD=15V and TA=25C.
Symbol
VDD Section VOP VDD-ON VDD-OFF IDD-OP IDD-GREEN VDD-OVP VDD-OVPHYST
Parameter
Continuously Operating Voltage Turn-On Threshold Voltage Turn-Off Threshold Voltage Operating Current Green-Mode Operating Supply Current VDD Over-Voltage Protection Level Hysteresis Voltage for VDD OVP VDD Over-Voltage-Protection Debounce Time Minimum Startup Voltage on HV Pin Supply Current Drawn from Pin HV Leakage Current after Startup
Conditions
Min.
Typ.
Max.
25
Units
V V V mA mA V
15 4.5
16 5.0 3.2 0.95 28
17 5.5 5.0 1.20
1.5 90
2.0 200
2.5 350 50
V s V mA A
tD-VDDOVP VHV-MIN IHV IHV-LC
HV Startup Current Source Section VDC=100V HV=500V, VDD=VDDOFF +1V 47 1.5 1.2 0.5 3.0 3.0
Oscillator Section fOSC tFHR fOSC-N-MIN fDV fDT Frequency Center Frequency Frequency Hopping Range 50 2.0 3 370 13 VDD=10~25V TA=-40C to +105C 1 2 15 53 2.5 kHz ms Hz kHz % %
Frequency Hopping Period Minimum Frequency at No-Load Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation Reference Voltage Green-Mode Starting Voltage on EA_V Green-Mode Ending Voltage on EA_V fOSC=-2kHz fOSC=1kHz RVS=20k
fOSC-CM-MIN Minimum Frequency at CCM
Voltage-Error-Amplifier Section VVR VN VG 2.475 2.500 2.5 0.5 1.4 10 90 VCOMR=1V 950 0.8 0.25 200 2.525 V V V V A ns ns V V
Voltage-Sense Section VBIAS-COMV Adaptive Bias Voltage Dominated by VCOMV Itc tPD tMIN-N VTH VTL IC Bias Current Propagation Delay to GATE Output Minimum On Time at No-Load Threshold Voltage for Current Limit Threshold Voltage on VS Pin Smaller than 0.5V Current-Sense Section
Continued on the following page...
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Electrical Characteristics (Continued)
Unless otherwise specified, VDD=15V and TA=25C.
Symbol
VIR VCOMR DCYMAX VOL VOH tr tf VCLAMP TOTP
Parameter
Reference Voltage COMR Pin for Cable Compensation Maximum Duty Cycle Output Voltage Low Output Voltage High Rising Time Falling Time Output Clamp Voltage Threshold Temperature for OTP
(3)
Conditions
Min.
2.475
Typ.
2.500 0.85
Max.
2.525
Units
V V
Current-Error-Amplifier Section Cable Compensation Section Gate Section 70 VDD=20V, Gate Sinks 10mA VDD=8V, Gate Sources 1mA CL=1nF CL=1nF VDD=25V 5 200 60 15 +140 250 100 18 75 80 1.5 % V V ns ns V C
Over-Temperature-Protection Section Note: 3. When the over-temperature protection is activated, the power system enters latch mode and output is disabled.
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Typical Performance Characteristics
17 5.5
16.6
5.3
16.2
VDD_OFF (V)
-40 -30 -15 0 25 50 75 85 100 125
VDD_ON (V)
5.1
15.8
4.9
15.4
4.7
15
4.5 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 6.
Turn-On Threshold Voltage (VDD-ON) vs. Temperature
Figure 7.
Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature
5
56 54 52 50 48 46 44
-40 -30 -15 0 25 50 75 85 100 125
4.2
IDD_OP (mA)
3.4
2.6
1.8
1
f osc (KHz)
-40
-30
-15
0
25
50
75
85
100
125
Temperature (C)
Temperature (C)
Figure 8.
Operating Current (IDD-OP) vs. Temperature
Figure 9.
Center Frequency (fOSC) vs. Temperature
2.525
1.2
2.515
1.12
VVR (V)
2.505
IDD_Green (mA)
1.04
2.495
0.96
2.485
0.88
2.475 -40 -30 -15 0 25 50 75 85 100 125
0.8 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 10. Reference Voltage (VVR) vs. Temperature
Figure 11. Green-Mode Operating Supply Current (IDD-GREEN) vs. Temperature
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(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Typical Performance Characteristics
450 420
16 15
f osc_CM_MIN (KHz)
-40 -30 -15 0 25 50 75 85 100 125
f osc_Green (Hz)
14 13 12 11 10 -40 -30 -15 0 25 50 75 85 100 125
390 360
330 300
Temperature (C)
Temperature (C)
Figure 12. Minimum Frequency at No Load (fOSC-N-MIN) vs. Temperature
Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN) vs. Temperature
3 2.5 2
1100 1050 1000 950 900 850 800
1.5 1 0.5 0 -40 -30 -15 0 25 50 75 85 100 125
tMIN_N (ns)
IHV (mA)
-40
-30
-15
0
25
50
75
85
100
125
Temperature (C)
Temperature (C)
Figure 14. Supply Current Drawn from Pin HV (IHV) vs. Temperature
Figure 15. Minimum On Time at No Load (tMIN-N) vs. Temperature
2.7
0.65
2.62
0.56
Vn (V)
2.46
Vg (V)
-40 -30 -15 0 25 50 75 85 100 125
2.54
0.47
0.38
2.38
0.29
2.3
0.2 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 16. Green Mode Starting Voltage on EA_V (VN) vs. Temperature
Figure 17. Green Mode Ending Voltage on EA_V (VG) vs. Temperature
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Typical Performance Characteristics
12 11.2 10.4 9.6 8.8 8 -40 -30 -15 0 25 50 75 85 100 125
Itc (A)
Temperature (C)
Figure 18. IC Bias Current (Itc) vs. Temperature
1.6 1.5
VBIAS_COMV (V)
1.4 1.3 1.2 1.1 1 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Figure 19. Output Clamp Voltage (VCLAMP) vs. Temperature
18
17.2
VCLAMP (V)
16.4
15.6
14.8
14 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Figure 20. Variation Test Voltage on COMR Pin for Cable Compensation (VCOMR) vs. Temperature
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Functional Description
Figure 21 shows the basic circuit diagram of a primaryside regulated flyback converter with typical waveforms shown in Figure 22. Generally, discontinuous conduction mode (DCM) operation is preferred for primary-side regulation since it allows better output regulation. The operation principles of DCM flyback converter are as follows: During the MOSFET on time (tON), input voltage (VDL) is applied across the primary-side inductor (Lm). Then, MOSFET current (Ids) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to be turned on. While the diode is conducting, the output voltage (Vo), together with diode forward voltage drop (VF), are 2 applied across the secondary-side inductor (LmxNs / 2 Np ) and the diode current (ID) decreases linearly from the peak value (IpkxNp/Ns) to zero. At the end of inductor current discharge time (tDIS), all the energy stored in the inductor has been delivered to the output. When the diode current reaches zero, the transformer auxiliary winding voltage (Vw) begins to oscillate by the resonance between the primary-side inductor (Lm) and the effective capacitor loaded across MOSFET. During the inductor current discharge time, the sum of output voltage and diode forward-voltage drop is reflected to the auxiliary winding side as (Vo+VF) x Na/Ns. Since the diode forward-voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time, where the diode current diminishes to zero. Thus, by sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to generate error voltage (VCOMV), which determines the duty cycle of the MOSFET in CV mode. Meanwhile, the output current can be estimated using the peak drain current and inductor current discharge time since output current is same as average of the diode current in steady state. The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the inductor discharge time (tDIS) and switching period (ts). This output information is compared with internal precise reference to generate error voltage (VCOMI), which determines the duty cycle of the MOSFET in CC mode. With Fairchild's innovative technique TRUECURRENTTM, constant current (CC) output can be precisely controlled. Among the two error voltages, VCOMV and VCOMI, the small one determines the duty cycle. Therefore, during constant voltage regulation mode, VCOMV determines the duty cycle while VCOMI is saturated to HIGH. During
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
constant current regulation mode, VCOMI determines the duty cycle while VCOMV is saturated to HIGH.
Np:Ns D + V DL VAC Gate
EA_I V COMI PWM Control V COMV EA_V Io Estimator Ref t DIS Detector Vo Estimator Ref
ID
Io + VO L O A D
Lm
+ VF -
-
I ds CS RCS Vs VDD RS1 RS2 NA + Vw -
Primary-Side Regulation Controller
Figure 21. Simplified PSR Flyback Converter Circuit
I pk
I pk
NP NS
I D.avg = I o
VF
NA NS
VO
NA NS
Figure 22. Key Waveforms of DCM Flyback Converter
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Cable Voltage Drop Compensation
When it comes to cellular phone charger applications, the battery is located at the end of cable, which causes, typically, several percentage of voltage drop on the actual battery voltage. FAN103 has a built-in cable voltage drop compensation, which provides a constant output voltage at the end of the cable over the entire load range in CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of voltage regulation error amplifier.
Operating Current
The operating current in FAN103 is as small as 3.2mA. The small operating current results in higher efficiency and reduces the VDD hold-up capacitance requirement. Once FAN103 enters deep-green mode, the operating current is reduced to 0.95mA, assisting the power supply in meeting power conservation requirements.
Green-Mode Operation
The FAN103 uses voltage regulation error amplifier output (VCOMV) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 23. The switching frequency decreases as load decreases. In heavy load conditions, the switching frequency is fixed at 50kHz. Once VCOMV decreases below 2.5V, the PWM frequency linearly decreases from 50kHz. When FAN103 enters into deep-green mode, the PWM frequency is reduced to a minimum frequency of 370Hz, gaining power saving to help meet international power conservation requirements. Figure 24. Frequency Hopping
High-Voltage Startup
Figure 25 shows the HV-startup circuit for FAN103 applications. The HV pin is connected to the line input or bulk capacitor through a resistor, RSTART (100k is recommended). During startup, the internal startup circuit in FAN103 is enabled. Meanwhile, line input supplies the current, ISTARTUP, to charge the hold-up capacitor, CDD, through RSTART. When the VDD voltage reaches VDD-ON, the internal startup circuit is disabled, blocking ISTARTUP from flowing into the HV pin. Once the IC turns on, CDD is the only energy source to supply the IC consumption current before the PWM starts to switch. Thus, CDD must be large enough to prevent VDD from dropping to VDD-OFF before the power can be delivered from the auxiliary winding.
Figure 23. Switching Frequency in Green Mode
Frequency Hopping
EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. FAN103 has an internal frequency hopping circuit that changes the switching frequency between 47kHz and 53kHz with a period, as shown in Figure 24. Figure 25. HV Startup Circuit
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at 16V and 5V, respectively. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable the FAN103. The hold-up capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer. VDD is not allowed to drop below 5V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor properly supplies VDD during startup.
Over-Temperature Protection (OTP)
The built-in temperature-sensing circuit shuts down PWM output if the junction temperature exceeds 140C.
Pulse-by-pulse Current Limit
When the sensing voltage across the current sense resistor exceeds the internal threshold of 0.8V, the MOSFET is turned off for the remainder of switching cycle. In normal operation, the pulse-by-pulse current limit is not triggered since the peak current is limited by the control loop.
Protections
The FAN103 has several self-protection functions, such as Over-Voltage Protection (OVP), Over-Temperature Protection (OTP), and Pulse-by-Pulse Current limit. All the protections are implemented as auto-restart mode. Once an abnormal condition occurs, switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD turn-off voltage of 5V, the internal startup circuit is enabled again, then the supply current drawn from HV pin charges the hold-up capacitor. When VDD reaches the turn-on voltage of 16V, FAN103 resumes normal operation. In this manner, the auto-restart alternately enables and disables the switching of the MOSFET until the abnormal condition is eliminated (see Figure 26).
Leading-Edge Blanking (LEB)
Each time the power MOSFET switches on, a turn-on spike occurs at the sense resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. Conventional RC filtering can be omitted. During this blanking period, the currentlimit comparator is disabled and cannot switch off the gate driver.
Gate Output
The FAN103 output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode to protect power MOSFET transistors against undesired over-voltage gate signals.
Built-in Slope Compensation
The sensed voltage across the current sense resistor is used for current mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillations due to peak-current mode control. The FAN103 has a synchronized, positive-slope ramp built-in at each switching cycle.
Noise Immunity
Noise from the current sense or the control signal can cause significant pulse-width jitter, particularly in continuous-conduction mode. While slope compensation helps alleviate these problems, further precautions should still be taken. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN103, and increasing the power MOS gate resistance is advised.
Figure 26. Auto Restart Operation
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents damage from overvoltage conditions. If the VDD voltage exceeds 28V at open-loop feedback condition, OVP is triggered and the PWM switching is disabled. The OVP has a de-bounce time (typically 200s) to prevent false triggering due to switching noises.
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3 www.fairchildsemi.com 12
FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Typical Application Circuit (Primary-Side-Regulated Flyback Charger)
Application Cell Phone Charger Fairchild Devices FAN103 Input Voltage Range 90~265VAC Output 5V/1A (5W) Output DC Cable AWG26, 1.8 Meter
Features
High efficiency (>68.17% at Full Load) Meeting EPS 2.0 Regulation with Enough Margin Low standby (Pin <30mW at No Load Condition) Tight output regulation (CV: 5%, CC: 5%)
6
74.00%
5
72.00%
4
70.00% 68.00% 66.00% 64.00% 62.00% 0.250 0.500 0.750 1.000
3
90Vac 230Vac 115Vac 264Vac
2
1
0 0 200 400 600 800 1000 1200 1400
Figure 27. Measured Efficiency and Output Regulation
Figure 28. Schematic of Typical Application Circuit
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3 www.fairchildsemi.com 13
FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Typical Application Circuit (Continued)
Transformer Specification
Core: EE16 Bobbin: EE16
Figure 29. Bobbin Winding Diagram Notes: 4. When W4R's winding is reversed winding, it must wind one layer. 5. When W2 is winding, put 1 layer tape after wind first layer.
NO
W1 W2 W3 W4R
TERMINAL S
4 3 1 7 9
F
5 1
WIRE
2UEW 0.23*2 2UEW 0.17*1 COPPER SHIELD TEX-E 0.6*1 CORE ROUNDING TAPE
Ts
15 40 40 37 1.2 9
INSULATION Ts
2 1 0 2 3 3 3
BARRIER Primary Seconds
Pin
Primary-Side Inductance Primary-Side Effective Leakage 13 13
Specification
1.75mH 5% 80H 5%
Remark
100kHz, 1V Short one of the secondary windings
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
Physical Dimensions
5.00 4.80 3.81
8 5
A
0.65
B
6.20 5.80
4.00 3.80
1 4
1.75
5.60
PIN ONE INDICATOR
(0.33)
1.27
0.25
M
CBA
1.27
LAND PATTERN RECOMMENDATION
0.25 0.10 1.75 MAX
C 0.10 0.51 0.33 0.50 x 45 0.25 C
SEE DETAIL A
0.25 0.19
OPTION A - BEVEL EDGE
R0.10 R0.10
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0 0.90 0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 30. 8-Lead, Small Outline Package (SOP-8)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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FAN103 -- Primary-Side-Regulation PWM Controller (PWM-PSR)
(c) 2010 Fairchild Semiconductor Corporation FAN103 * Rev. 1.0.3
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